The present invention relates in general to DC power supply circuits and components therefor, and is particularly directed to a new and improved feed forward enabled pulse width modulator (PWM) circuit, that is configured to operate at a constant switching frequency, and maintains a fixed deadtime by adjusting timing capacitor discharge current in accordance with variation in input voltage. This serves to maintain the deadtime interval of the PWM signal predictably constant.
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (battery) power sources, such as a pulse width modulation (PWM)-based, DC-DC converter. This type of converter contains a PWM signal generator that supplies a synchronous PWM signal to a switching circuit driver. The switching circuit drive, in turn, controls the on-time and off-time of electronic power switching devices as is known in the art.
The pulse width modulator (PWM) circuit itself is typically implemented using a comparator which compares an output signal from a control amplifier with a ramp waveform signal. The comparator output has a first state, when the output signal is greater than the ramp voltage and a second state when the voltage level of the ramp waveform has a value greater than the output voltage of the control amplifier. Thus, the duty cycle of the PWM waveform may be controlled by the output voltage of the control amplifier.
The ramp waveform itself may be generated by charging a timing capacitor with a current that is derived from the input voltage, using a resistor coupled between the input voltage source and a first terminal of the capacitor. In this xe2x80x98feed forwardxe2x80x99 type of circuit, since the resistor is coupled to the same input voltage source that is supplying energy to the load, a variation in input voltage level causes an associated variation in charging current to the capacitor. Thus, an increase in the voltage level of the ramp signal will cause an increase in ramp slope, which results in the ramp voltage becoming greater than the voltage level of the control amplifier output signal in a relatively shorter period of time.
Conversely, for a decrease in input voltage, the slope of the ramp signal voltage decreases, so that it takes a longer period of time for the voltage level of the ramp signal to reach the control amplifier output voltage level. This results in a relatively longer PWM output pulse. Thus, when the input voltage is relatively large, the output PWM generator""s output pulse-width is relatively narrow, and when the input voltage is relatively small the PWM generator""s output pulse is relatively wide. Since, energy is proportional to the product of the voltage amplitude and the time duration that the voltage is applied to the load, such a PWM architecture is ideally intended to deliver constant energy to the output regardless of the input voltage.
This type of a circuit may be operated at a constant switching frequency, by coupling a switch in parallel with the capacitor terminals and operating the switch with a fixed frequency oscillator. The switch should be switched for a duration of time long enough to discharge the capacitor. In the on-state, the switch provides a very low impedance, so that the capacitor rapidly discharges in an amount of time which is negligible with respect to the time of a full period.
In such a circuit however, it is often desirable to provide a time interval during which the switch is guaranteed to be off, known as deadtime, such as may be used to allow time for the resetting of magnetic circuit components within the power supply. Thus, modulation of the PWM generator""s duty cycle is limited to insure that there always exists a deadtime period.
In order to retard discharge of the timing capacitor through the switch a resistor may be coupled between a first terminal of the switch and a first terminal of the capacitor. The circuit may thus be configured such that while the timing capacitor is discharging an output switching device (e.g., transistor) may be turned off. Thus, by selecting the discharge resistor to have a predetermined value, a selected deadtime may be programmed into the circuit.
Unfortunately, it is difficult to provide a circuit which operates at a relatively fixed switching frequency and which has both voltage feed forward circuit characteristics and a duty cycle clamp. This difficulty arises due to the fact that the variable charging time of the timing capacitor tends to move the discharge time with respect to the total switching period. Either the switch frequency may vary or, at low input voltages, the capacitor may not become completely discharged by the end of the period. This results in a reduction in the deadtime interval.
In an effort to remedy this situation, the U.S. Patent to Mammano et al, U.S. Pat. No. 5,414,342 (hereinafter referred to as the ""342 Patent) proposes a PWM circuit architecture, in which the timing capacitor charging current and upper threshold voltage are made proportional to input voltage. As a result, when the ramp slope increases with an increase in input voltage, the upper threshold will also increase, so that duty cycle is maintained constant. Discharge time is controlled in accordance with the resistance of a discharge resistor for a particular value of timing capacitor. A problem with this type of circuit is the fact that it is not readily suited for PWM-based power supply circuits, such as zero voltage switching (ZVS) applications, which mandate a fixed deadtime to prevent multiple switching devices that are driven by the PWM signal from being on at the same time.
In accordance with the present invention, this shortcoming is effectively remedied by augmenting the proportional-to-input voltage charging current functionality employed by the PWM circuit described in the ""342 Patent to include proportional-to-input voltage discharging current functionality. To this end, the PWM waveform generator of the invention couples an input port, to which an input voltage is applied, through a buffer amplifier to respective charging and discharging control resistors. These resistors develop respective currents proportional to the input voltage, which are used to controllably charge and discharge a timing capacitor.
The buffer amplifier output is summed with a (zero or non-zero) valley threshold voltage reference to create a peak threshold voltage proportional to the input voltage. The peak threshold voltage is applied as a reference to a first comparator, and the valley threshold voltage is applied as a reference to a second comparator. The inputs to these comparators are coupled to monitor the voltage developed across a timing capacitor. The outputs of the comparators are used to control the state of a switch control latch (flip-flop), so as to form a fixed switching frequency oscillator, which controls the operation of respective capacitor charging and discharging switches. These switches are coupled with respective charging and discharging current sources, that mirror the currents through the respective charging and discharging control resistors.
In operation, at the start of a PWM ramp interval, the states of the comparators are such that the switch control flip-flop closes the charging switch and opens the discharging switch, so that charging current proportional to the input voltage is applied to the timing capacitor. This starts the rise time of the PWM ramp signal. When the ramp signal reaches the control voltage applied to an output PWM comparator, the output of that comparator goes high. When the voltage across the timing capacitor reaches the peak threshold voltage, the states of the latch outputs are reversed. As a result, the charging switch is opened, terminating the flow of charging current to the capacitor, and the discharging switch is closed.
With the discharging switch closed, the timing capacitor is discharged by a current that is proportional to input voltage. As in the case of the rise time of the ramp signal, the higher the input voltage, the greater the slope of the fall time of the ramp signal, whereas the lower the input voltage, the more gradual the fall time of the ramp signal. In either case, because the fall time of the ramp signal is proportional to the input voltage, the deadtime interval of the PWM signal is predictably constant, as intended. As the timing capacitor is discharged by the discharging current source, its voltage eventually reaches the valley threshold voltage which resets the flip-flop and starts the rise time of the next PWM waveform cycle.